The present invention relates to binary MOS ripple-carry parallel adders/subtracters which are integrated using enhancement-mode insulated-gate field-effect transistors and with which a plurality of numbers each represented in an n-digit binary code can be added or subtracted from each other by successive summation forming partial sums. The formation of partial sums of the numbers A, B, C . . . Z takes place according to the following recursive formula: EQU A+B+C+ . . . Z=((A+B)+C) . . . +Z=(Sb+C) . . . +Z=Sc . . . +Z=Sz.
Each partial sum is formed in a parallel adder/subtracter comprising an adder/subtracter stage per digit of each partial sum. The adder/subtracter stage, in turn, includes a switching element taking into account the sign of the number, i.e., of a switching element for switching from addition to subtraction which has a first input for a switching signal and a second input for that one of two digit signals of the number which serves as the subtrahend in case of subtraction. Furthermore, the adder/subtracter stage includes a full adder having a first input receiving directly the digit signal serving as the minuend in case of subtraction, and a second input connected to the output of the switching element.
Parallel adders/subtracters with adder/subtracter stages of this kind are described in a book by A. Shah, et al, "Integrierte Schaltungen in Digitalen Systemen", Vol. 2, Basel, 1977, pages 124 to 129, particularly FIG. IX.28 on page 125. On pages 107 to 109 of that book, so-called parallel counters for adding a plurality of numbers are explained in a general form. The parallel counter shown there in FIG. IX.18, which is referred to as a "(5,3) parallel counter" and is capable of summing five single-digit numbers, includes three sets of series-connected logic gates of different kind. On pages 87 to 103, the book gives information on commercially available bipolar integrated circuits for adders.
Direct application of the fundamental principles of conventional ripple-carry parallel adders/subtracters, explained with reference to bipolar integrated circuits, to integrated circuits using insulated-gate field-effect transistors, i.e., to so-called MOS circuits, is not readily possible because MOS technology differs widely from bipolar technology in some respects.